In recent years, lower power consumption of a logic circuit used in an electronic apparatus has been desired, as various electronic apparatuses equipped with logic circuits have been mobilized. A logic circuit used for an electronic apparatus is configured of a semiconductor integrated circuit such as a complementary metal oxide semiconductor (CMOS) transistor in many cases. In recent years, CMOS manufacturing processes have been finer, as represented by a reduction in gate width and thinning of oxide films. As the manufacturing processes have thus become finer, a leakage current in a CMOS transistor has increased, and it has been difficult to ignore power consumption caused thereby. As a remedy therefor, there is a technique called power gating that interrupts power supply to a logic circuit in a period in which the logic circuit is not in operation. For example, PTL 1 to PTL 4 each propose a circuit that reduces a leakage current by using the power gating.